As semiconductor devices such as logic and memory devices continue to scale to smaller dimensions, the use of conventional processing and materials to fabricate semiconductor devices is increasingly problematic. In one example, new approaches for doping semiconductor structures are being investigated to supplant ion implantation. For example, in future technology generations, transistors may be formed of three-dimensional structures, such as horizontal gate all around structures (HGAA) where active regions are formed using so-called nanowires. Doping of such nanowires becomes a challenge using known implantation techniques, since portions of the nanowire do not present line-of-sight surfaces easily accessed by implanting ions. Plasma immersion techniques may not be suitable for such structures where the dimensions may be on the order of nanometers or a few tens of nanometers. The growth of doped high quality epitaxial semiconductor layers to provide dopants on nanowires may also be difficult due to the geometry of nanowires, as well as the high level of dopant needed.
With respect to these and other considerations the present disclosure has been provided.